Semiconductor devices continue to shrink in size and increase in complexity. As a result, a semiconductor device requires very close spacing of interconnect lines, and often requires a plurality of conductive layers for interconnecting the circuits formed therein. Dielectric layers separate the conductive layers and vias. Capacitance and cross talk between adjacent interconnect lines becomes more of a problem as the device geometries shrink and densities increase.
Typically, a dielectric layer includes silicon dioxide. Attempts have been made to replace silicon dioxide with a low dielectric constant material, i.e., with a material having a dielectric constant less than 4. The lower the dielectric constant, the better the insulator, thus lowering the capacitance between closely spaced interconnect lines. A dielectric material having a dielectric constant less than about 3.5 sufficiently reduces the capacitance between interconnect lines in typical sub-micron circuits.
Unfortunately, a low dielectric constant material may have low mechanical strength and poor dimensional stability. These characteristics require extra processing steps when forming a via through a low dielectric constant material. Porous sidewalls of the via may cause stability and adhesion problems during barrier and seed layer deposition. One approach to these problems is to perform a coating deposition step after via etch and clean, but prior to deposition of the barrier and seed layers.
The coating deposition forms a layer on the porous sidewalls of the via making them conformal. This layer fills in the porous openings in the sidewalls thus allowing the barrier and seed layers to be conformal when deposited. Unfortunately, deposition of the coating layer adds extra processing steps when making a semiconductor device. As discussed above, this added step is performed after the coating on the sidewalls of the via has been etched and cleaned. During the coating deposition step, the bottom of the via is also coated. Consequently, another processing step is required to etch and clean the bottom of the via.